The present invention relates to Read Only Memory (ROM) devices and more particularly to optimizing the read time of a low voltage ROM device.
A ROM device includes a ROM array including a plurality of bit line columns and a plurality of word lines. Each of the bit line columns is connected to a plurality of bit lines. Each of the bit line columns includes a plurality of bit cells. The bit cells are connected to the bit lines and the word lines. The bit cells store binary data. The bit line columns are connected to one or more column multiplexers. The column multiplexers are further connected to one or more sense amplifiers. The bit lines are pre-charged by a pull-up bit line signal and the data stored in the bit cells is read by the one or more sense amplifiers. Further, the bit lines are discharged by a pull-down bit line signal.
Presently, there is a desire that electronic devices consume less power, so there is a demand for electronic devices that operate at lower power levels. For ROM devices, operating at low voltage decreases operating frequency. This reduction in the operating frequency increases the data read time, which degrades performance.
It would be advantageous to have a ROM device with an improved read time when the ROM is operating at a low supply voltage.